A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps
نویسندگان
چکیده
This paper presents a variable delay line DLL circuit implemented in a 0.8 m CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The DLL circuit is capable of reducing clock skew from 1-3ns to below 500ps for clock frequencies from 50Mhz to 150Mhz.
منابع مشابه
A 0 . 8 m CMOS Delayed Locked Loop for Sub - 500 ps Clock
Yong-Bin Kim* Tom Chen** *Microelectronics Division Samsung Electronics Co. San Jose, CA, USA **Department of Electrical Engineering Colorado State Univ. Fort Collins, CO 80523, USA Abstract This paper describes a CMOS variable delay line Delay Locked Loop(DLL) circuit speci cally designed for reducing clock skew on DRAM/Logic merged integrated circuit using 0.6 m CMOS process. A phase detector...
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